library IEEE;
use IEEE.STD_LOGIC_1164.ALL;


entity adder_4 is
    Port ( a : in  STD_LOGIC_VECTOR (3 downto 0);
           b : in  STD_LOGIC_VECTOR (3 downto 0);
           carryIn : in  STD_LOGIC;
           sum : out  STD_LOGIC_VECTOR (3 downto 0);
           carryOut : out  STD_LOGIC);
end adder_4;

architecture Behavioral of adder_4 is
begin
	sum(0) <= a(0) xor b(0) xor carryIn;
	sum(1) <= a(1) xor b(1) xor ((a(0) and b(0)) or (carryIn and (a(0) or b(0))));
	sum(2) <= a(2) xor b(2) xor ((a(1) and b(1)) or (((a(0) and b(0)) or (carryIn and (a(0) or b(0)))) and (a(1) or b(1))));
	sum(3) <= a(3) xor b(3) xor ((a(2) and b(2)) or (((a(1) and b(1)) or (((a(0) and b(0)) or (carryIn and (a(0) or b(0)))) and (a(1) or b(1)))) and (a(2) or b(2))));
	carryOut <= (a(3) and b(3)) or (((a(2) and b(2)) or (((a(1) and b(1)) or (((a(0) and b(0)) or (carryIn and (a(0) or b(0)))) and (a(1) or b(1)))) and (a(2) or b(2)))) and (a(3) or b(3)));
end Behavioral;

